View MA80C186XL16_8481446.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

* other brands and names are the property of their respective owners. information in this document is provided in connection with intel products. intel assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of intel products except as provided in intel's terms and conditions of sale for such products. intel retains the right to make changes to these specifications at any time, without notice. microcomputer products may have minor variations to this specification known as errata. march 1995 copyright ? intel corporation, 1996 order number: 271276-002 m80c186xl20, 16, 12, 10 16-bit high-integration embedded processor y low power, full static version of m80c186 y operation modes: e enhanced mode e dram refresh control unit e power-save mode e direct interface to 80c187 e compatible mode e nmos 80186 pin-for-pin replacement for non-numerics applications y integrated feature set e static, modular cpu e clock generator e 2 independent dma channels e programmable interrupt controller e 3 programmable 16-bit timers e dynamic ram refresh control unit e programmable memory and peripheral chip select logic e programmable wait state generator e local bus controller e power-save mode e system-level testing support (high impedance test mode) y completely object code compatible with existing 8086/8088 software and has 10 additional instructions over 8086/8088 y speed versions available e 20 mhz (m80c186xl20) e 16 mhz (m80c186xl16) e 12.5 mhz (m80c186xl12) e 10 mhz (m80c186xl) y direct addressing capability to 1 mbyte memory and 64 kbyte i/o y complete system development support e all 8086 and 80c186 software development tools can be used for m80c186xl system development e asm 86 assembler, pl/m-86, pascal-86, fortran-86, ic-86 and system utilities e in-circuit-emulator (ice tm -186) y available in 68-pin: e ceramic pin grid array (pga) y military temperature range: e b 55 cto a 125 c(t c ) the intel m80c186xl is a modular core re-implementation of the m80c186 microprocessor. it offers higher speed and lower power consumption than the standard m80c186 but maintains 100% clock-for-clock func- tional compatibility. packaging and pinout are also identical. 271276 1
m80c186xl20, 16, 12, 10 16-bit high integration embedded processor contents page introduction 10 m80c186xl base architecture 10 m80c186xl clock generator 10 bus interface unit 11 m80c186xl peripheral architecture 11 chip-select/ready generation logic 11 dma unit 12 timer/counter unit 12 interrupt control unit 12 enhanced mode operation 12 queue-status mode 12 dram refresh control unit 13 power-save control 13 interface for 80c187 math coprocessor 13 once test mode 13 absolute maximum ratings 14 dc characteristics 14 contents page ac characteristics 16 major cycle timings (read cycle) 16 major cycle timings (write cycle) 18 major cycle timings (interrupt acknowledge cycle) 20 software halt cycle timings 22 clock timings 23 ready, peripheral and queue status timings 25 reset and hold/hlda timings 27 ac timing waveforms 33 explanation of the ac symbols 36 derating curves 37 m80c186xl execution timings 38 instruction set summary 39 footnotes 44 2
m80c186xl figure 1. m80c186xl block diagram 271276 2 3
m80c186xl ceramic pin grid array pins facing up pins facing down 271276 3 note: xxxxxxxxa indicates the intel fpo number. figure 2. m80c186xl pinout diagrams 4
m80c186xl table 1. m80c186xl pin description symbol pga type name and function pin no. v cc 9 i system power: a 5 volt power supply. 43 i v ss 26 i system ground. 60 i reset 57 o reset output indicates that the m80c186xl cpu is being reset, and can be used as a system reset. it is active high, synchronized with the processor clock, and lasts an integer number of clock periods corresponding to the length of the res signal. reset goes inactive 2 clockout periods after res goes inactive. when tied to the test / busy pin, reset forces the m80c186xl into enhanced mode. reset is not floated during bus hold. x1 59 i crystal inputs x1 and x2 provide external connections for a fundamental mode or third overtone parallel resonant crystal for the x2 58 o internal oscillator. x1 can connect to an external clock instead of a crystal. in this case, minimize the capacitance on x2. the input or oscillator frequency is internally divided by two to generate the clock signal (clkout). clkout 56 o clock output provides the system with a 50% duty cycle waveform. all device pin timings are specified relative to clkout. clkout is active during reset and bus hold. res 24 i an active res causes the m80c186xl to immediately terminate its present activity, clear the internal logic, and enter a dormant state. this signal may be asynchronous to the m80c186xl clock. the m80c186xl begins fetching instructions approximately 6 (/2 clock cycles after res is returned high. for proper initialization, v cc must be within specifications and the clock signal must be stable for more than 4 clocks with res held low. res is internally synchronized. this input is provided with a schmitt-trigger to facilitate power-on res generation via an rc network. test /busy 47 i/o the test pin is sampled during and after reset to determine whether the m80c186xl is to enter compatible or enhanced mode. enhanced mode requires test to be high on the rising edge of res and low four clkout cycles later. any other combination will place the m80c186xl in compatible mode. during power-up, active res is required to configure test /busy as an input. a weak internal pullup ensures a high state when the input is not externally driven. test ein compatible mode this pin is configured to operate as test . this pin is examined by the wait instruction. if the test input is high when wait execution begins, instruction execution will suspend. test will be resampled every five clocks until it goes low, at which time execution will resume. if interrupts are enabled while the m80c186xl is waiting for test , interrupts will be serviced. busyein enhanced mode, this pin is configured to operate as busy. the busy input is used to notify the m80c186xl of math coprocessor activity. floating point instructions executing in the m80c186xl sample the busy pin to determine when the math coprocessor is ready to accept a new command. busy is active high. 5
m80c186xl table 1. m80c186xl pin description (continued) symbol pga type name and function pin no. tmr in 0 20 i timer inputs are used either as clock or control signals, depending upon the programmed timer mode. these inputs are tmr in 1 21 i active high (or low-to-high transitions are counted) and internally synchronized. timer inputs must be tied high when not being used as clock or retrigger inputs. tmr out 0 22 o timer outputs are used to provide single pulse or continous waveform generation, depending upon the timer mode selected. tmr out 1 23 o these outputs are not floated during a bus hold. drq0 18 i dma request is asserted high by an external device when it is ready for dma channel 0 or 1 to perform a transfer. these drq1 19 i signals are level-triggered and internally synchronized. nmi 46 i the non-maskable interrupt input causes a type 2 interrupt. an nmi transition from low to high is latched and synchronized internally, and initiates the interrupt at the next instruction boundary. nmi must be asserted for at least one clkout period. the non-maskable interrupt cannot be avoided by programming. int0 45 i maskable interrupt requests can be requested by activating one of these pins. when configured as inputs, these pins are active int1/select 44 i high. interrupt requests are synchronized internally. int2 and int2/inta0 42 i/o int3 may be configured to provide active-low interrupt- int3/inta1 /irq 41 i/o acknowledge output signals. all interrupt inputs may be configured to be either edge- or level-triggered. to ensure recognition, all interrupt requests must remain active until the interrupt is acknowledged. when slave mode is selected, the function of these pins changes (see interrupt controller section of this data sheet). a19/s6 65 o address bus outputs (16 19) and bus cycle status (3 6) indicate the four most significant address bits during t 1 . these a18/s5 66 o signals are active high. a17/s4 67 o a16/s3 68 o during t 2 ,t 3 ,t w and t 4 , the s6 pin is low to indicate a cpu- initiated bus cycle or high to indicate a dma-initiated or refresh bus cycle. during the same t-states, s3, s4 and s5 are always low. these outputs are floated during bus hold or reset. ad15 1 i/o address/data bus (0 15) signals constitute the time multiplexed memory or i/o address (t 1 ) and data (t 2 ,t 3 ,t w and t 4 ) bus. ad14 3 i/o the bus is active high. a 0 is analogous to bhe for the lower ad13 5 i/o byte of the data bus, pins d 7 through d 0 . it is low during t 1 ad12 7 i/o when a byte is to be transferred onto the lower portion of the bus ad11 10 i/o in memory or i/o operations. these pins are floated during a bus ad10 12 i/o hold or reset. ad9 14 i/o ad8 16 i/o ad7 2 i/o ad6 4 i/o ad5 6 i/o ad4 8 i/o ad3 11 i/o ad2 13 i/o ad1 15 i/o ad0 17 i/o 6
m80c186xl table 1. m80c186xl pin description (continued) symbol pga type name and function pin no. bhe 64 o the bhe (bus high enable) signal is analogous to a0 in that it is used to enable data on to the most significant half of the data bus, pins d15 d8. bhe will be low during t 1 when the upper byte is transferred and will remain low through t 3 and t w . bhe does not need to be latched. bhe will float during hold or reset. in enhanced mode, bhe will also be used to signify dram refresh cycles. a refresh cycle is indicated by both bhe and a0 being high. bhe and a0 encodings bhe a0 function value value 0 0 word transfer 0 1 byte transfer on upper half of data bus (d15 d8) 1 0 byte transfer on lower half of data bus (d 7 d 0 ) 1 1 refresh ale/qs0 61 o address latch enable/queue status 0 is provided by the m80c186xl to latch the address. ale is active high, with addresses guaranteed valid on the trailing edge. wr /qs1 63 o write strobe/queue status 1 indicates that the data on the bus is to be written into a memory or an i/o device. it is active low, and floats during bus hold or reset. when the m80c186xl is in queue status mode, the ale/qs0 and wr /qs1 pins provide information about processor/instruction queue interaction. qs1 qs0 queue operation 0 0 no queue operation 0 1 first opcode byte fetched from the queue 1 1 subsequent byte fetched from the queue 1 0 empty the queue rd /qsmd 62 o/i read strobe is an active low signal which indicates that the m80c186xl is performing a memory or i/o read cycle. it is guaranteed not to go low before the a/d bus is floated. an internal pull-up ensures that rd /qsmd is high during reset. following reset the pin is sampled to determine whether the m80c186xl is to provide ale, rd , and wr , or queue status information. to enable queue status mode, rd must be connected to gnd. rd will float during bus hold. ardy 55 i asynchronous ready informs the m80c186xl that the addressed memory space or i/o device will complete a data transfer. the ardy pin accepts a rising edge that is asynchronous to clkout and is active high. the falling edge of ardy must be synchronized to the m80c186xl clock. connecting ardy high will always assert the ready condition to the cpu. if this line is unused, it should be tied low to yield control to the srdy pin. srdy 49 i synchronous ready informs the m80c186xl that the addressed memory space or i/o device will complete a data transfer. the srdy pin accepts an active-high input synchronized to clkout. the use of srdy allows a relaxed system timing over ardy. this is accomplished by elimination of the one-half clock cycle required to internally synchonize the ardy input signal. connecting srdy high will always assert the ready condition to the cpu. if this line is unused, it should be tied low to yield control to the ardy pin. 7
m80c186xl table 1. m80c186xl pin description (continued) symbol pga type name and function pin no. lock 48 o lock output indicates that other system bus masters are not to gain control of the system bus. lock is active low. the lock signal is requested by the lock prefix instruction and is activated at the beginning of the first data cycle associated with the instruction immediately following the lock prefix. it remains active until the completion of that instruction. no instruction prefetching will occur while lock is asserted. lock floats during bus hold or reset. s0 52 o bus cycle status s0 s2 are encoded to provide bus-transaction information: s1 53 o s2 54 o m80c186xl bus cycle status information s2 s1 s0 bus cycle initiated 0 0 0 interrupt acknowledge 0 0 1 read i/o 0 1 0 write i/o 0 1 1 halt 1 0 0 instruction fetch 1 0 1 read data from memory 1 1 0 write data to memory 1 1 1 passive (no bus cycle) the status pins float during hold. s2 may be used as a logical m/io indicator, and s1 as a dt/r indicator. hold 50 i hold indicates that another bus master is requesting the local bus. the hold input is active high. the m80c186xl generates hlda (high) in hlda 51 o response to a hold request. simultaneous with the issuance of hlda, the m80c186xl will float the local bus and control lines. after hold is detected as being low, the m80c186xl will lower hlda. when the m80c186xl needs to run another bus cycle, it will again drive the local bus and control lines. in enhanced mode, hlda will go low when a dram refresh cycle is pending in the m80c186xl and an external bus master has control of the bus. it will be up to the external master to relinquish the bus by lowering hold so that the m80c186xl may execute the refresh cycle. ucs 34 o/i upper memory chip select is an active low output whenever a memory reference is made to the defined upper portion (1k 256k block) of memory. ucs does not float during bus hold. the address range activating ucs is software programmable. ucs and lcs are sampled upon the rising edge of res . if both pins are held low, the m80c186xl will enter once mode. in once mode all pins assume a high impedance state and remain so until a subsequent reset. ucs has a weak internal pullup that is active during reset to ensure that the m80c186xl does not enter once mode inadvertently. lcs 33 o/i lower memory chip select is active low whenever a memory reference is made to the defined lower portion (1k 256k) of memory. lcs does not float during bus hold. the address range activating lcs is software programmable. 8
m80c186xl table 1. m80c186xl pin description (continued) symbol pga type name and function pin no. lcs ucs and lcs are sampled upon the rising edge of res . if both pins are held low, the m80c186xl will enter once mode. in once (continued) mode all pins assume a high impedance state and remain so until a subsequent reset. lcs has a weak internal pullup that is active only during reset to ensure that the m80c186xl does not enter once mode inadvertently. mcs0 /pereq 38 o/i mid-range memory chip select signals are active low when a memory reference is made to the defined mid-range portion of mcs1 /error 37 o/i memory (8k 512k). these lines do not float during bus hold. the mcs2 36 o address ranges activating mcs0 3 are software programmable. mcs3 /nps 35 o in enhanced mode, mcs0 becomes a pereq input (processor extension request). when connected to the math coprocessor, this input is used to signal the m80c186xl when to make numeric data transfers to and from the coprocessor. mcs3 becomes nps (numeric processor select) which may only be activated by communication to the 80c187. mcs1 becomes error in enhanced mode and is used to signal numerics coprocessor errors. mcs0 /pereq and mcs1 /error have weak internal pullups which are active during reset. pcs0 25 o peripheral chip select signals 0 4 are active low when a reference is made to the defined peripheral area (64k byte i/o or 1 pcs1 27 o mbyte memory space). these lines do not float during bus hold. pcs2 28 o the address ranges activating pcs0 4 are software pcs3 29 o programmable. pcs4 30 o pcs5 /a1 31 o peripheral chip select 5 or latched a1 may be programmed to provide a sixth peripheral chip select, or to provide an internally latched a1 signal. the address range activating pcs5 is software- programmable. pcs5 /a1 does not float during bus hold. when programmed to provide latched a1, this pin will retain the previously latched value during hold. pcs6 /a2 32 o peripheral chip select 6 or latched a2 may be programmed to provide a seventh peripheral chip select, or to provide an internally latched a2 signal. the address range activating pcs6 is software- programmable. pcs6 /a2 does not float during bus hold. when programmed to provide latched a2, this pin will retain the previously latched value during hold. dt/r 40 o data transmit/receive controls the direction of data flow through an external data bus transceiver. when low, data is transferred to the m80c186xl. when high the m80c186xl places write data on the data bus. dt/r floats during a bus hold or reset. den 39 o data enable is provided as a data bus transceiver output enable. den is active low during each memory and i/o access (including 80c187 access). den is high whenever dt/r changes state. during reset, den is driven high for one clock, then floated. den also floats during hold. n.c. e e not connected. to maintain compatibility with future products, do not connect to these pins. 9
m80c186xl 271276 4 (3a) 271276 5 (3b) note 1: xtal frequency l1 value 20 mhz 12.0 m h g 20% 25 mhz 8.2 m h g 20% 32 mhz 4.7 m h g 20% 40 mhz 3.0 m h g 20% lc network is only required when using a third overtone crystal. figure 3. m80c186xl oscillator configurations (see text) introduction the following functional description describes the base architecture of the m80c186xl. the m80c186xl is a very high integration 16-bit micro- processor. it combines 15 20 of the most common microprocessor system components onto one chip. the m80c186xl is object code compatible with the 8086/8088 microprocessors and adds 10 new in- struction types to the 8086/8088 instruction set. the m80c186xl has two major modes of operation, compatible and enhanced. in compatible mode the m80c186xl is completely compatible with nmos 80186, with the exception of 8087 support. the en- hanced mode adds three new features to the system design. these are power-save control, dynamic ram refresh, and an asynchronous numerics co- processor interface. m80c186xl base architecture m80c186xl clock generator the m80c186xl provides an on-chip clock genera- tor for both internal and external clock generation. the clock generator features a crystal oscillator, a divide-by-two counter, synchronous and asynchro- nous ready inputs, and reset circuitry. the m80c186xl oscillator circuit is designed to be used either with a parallel resonant fundamental or third-overtone mode crystal, depending upon the frequency range of the application. this is used as the time base for the m80c186xl. the output of the oscillator is not directly available outside the m80c186xl. the recommended crystal configuration is shown in figure 3b. when used in third-overtone mode, the tank circuit is recommend- ed for stable operation. alternately, the oscillator may be driven from an external source as shown in figure 3a. the crystal or clock frequency chosen must be twice the required processor operating frequency due to the internal divide by two counter. this counter is used to drive all internal phase clocks and the exter- nal clkout signal. clkout is a 50% duty cycle processor clock and can be used to drive other sys- tem components. all ac timings are referenced to clkout. intel recommends the following values for crystal se- lection parameters. temperature range: application specific esr (equivalent series resistance): 60 x max c 0 (shunt capacitance of crystal): 7.0 pf max c 1 (load capacitance): 20 pf g 5pf drive level: 2 mw max 10
m80c186xl bus interface unit the m80c186xl provides a local bus controller to generate the local bus control signals. in addition, it employs a hold/hlda protocol for relinquishing the local bus to other bus masters. it also provides outputs that can be used to enable external buffers and to direct the flow of data on and off the local bus. the bus controller is responsible for generating 20 bits of address, read and write strobes, bus cycle status information and data (for write operations) in- formation. it is also responsible for reading data from the local bus during a read operation. synchro- nous and asynchronous ready input pins are provid- ed to extend a bus cycle beyond the minimum four states (clocks). the m80c186xl bus controller also generates two control signals (den and dt/r ) when interfacing to external transceiver chips. this capability allows the addition of transceivers for simple buffering of the multiplexed address/data bus. during reset the local bus controller will perform the following action: # drive den ,rd and wr high for one clock cy- cle, then float them. # drive s0 s2 to the inactive state (all high) and then float. # drive lock high and then float. # float ad0 15, a16 19, bhe , dt/r . # drive ale low # drive hlda low. rd /qsmd , ucs , lcs , mcs0 /pereq, mcs1 / error and test /busy pins have internal pullup devices which are active while res is applied. ex- cessive loading or grounding certain of these pins causes the m80c186xl to enter an alternative mode of operation: # rd /qsmd low results in queue status mode. # ucs and lcs low results in once mode. # test /busy low (and high later) results in en- hanced mode. m80c186xl peripheral architecture all the m80c186xl integrated peripherals are con- trolled by 16-bit registers contained within an inter- nal 256-byte control block. the control block may be mapped into either memory or i/o space. internal logic will recognize control block addresses and re- spond to bus cycles. an offset map of the 256-byte control register block is shown in figure 4. chip-select/ready generation logic the m80c186xl contains logic which provides pro- grammable chip-select generation for both memo- ries and peripherals. in addition, it can be pro- grammed to provide ready (or wait state) genera- tion. it can also provide latched address bits a1 and a2. the chip-select lines are active for all memory and i/o cycles in their programmed areas, whether they be generated by the cpu or by the integrated dma unit. the m80c186xl provides 6 memory chip select out- puts for 3 address areas; upper memory, lower memory, and midrange memory. one each is provid- ed for upper memory and lower memory, while four are provided for midrange memory. offset relocation register feh dma descriptors channel 1 dah d0h dma descriptors channel 0 cah c0h chip-select control registers a8h a0h time 2 control registers 66h 60h time 1 control registers 5eh 58h time 0 control registers 56h 50h interrupt controller registers 3eh 20h figure 4. internal register map the m80c186xl provides a chip select, called ucs , for the top of memory. the top of memory is usually used as the system memory because after reset the m80c186xl begins executing at memory location ffff0h. 11
m80c186xl the m80c186xl provides a chip select for low memory called lcs . the bottom of memory con- tains the interrupt vector table, starting at location 00000h. the m80c186xl provides four mcs lines which are active within a user-locatable memory block. this block can be located within the m80c186xl 1 mbyte memory address space exclusive of the areas de- fined by ucs and lcs . both the base address and size of this memory block are programmable. the m80c186xl can generate chip selects for up to seven peripheral devices. these chip selects are ac- tive for seven contiguous blocks of 128 bytes above a programmable base address. the base address may be located in either memory or i/o space. the m80c186xl can generate a ready signal in- ternally for each of the memory or peripheral cs lines. the number of wait states to be inserted for each peripheral or memory is programmable to pro- vide 0 3 wait states for all accesses to the area for which the chip select is active. in addition, the m80c186xl may be programmed to either ignore external ready for each chip-select range individu- ally or to factor external ready with the integrated ready generator. upon reset, the chip-select/ready logic will per- form the following actions: # all chip-select outputs will be driven high. # upon leaving reset, the ucs line will be pro- grammed to provide chip selects to a 1k block with the accompanying ready control bits set at 011 to insert 3 wait states in conjunction with ex- ternal ready (i.e., umcs resets to fffbh). # no other chip select or ready control registers have any predefined values after reset. they will not become active until the cpu accesses their control registers. dma unit the m80c186xl dma controller provides two inde- pendent high-speed dma channels. data transfers can occur between memory and i/o spaces (e.g., memory to i/o) or within the same space (e.g., memory to memory or i/o to i/o). data can be transferred either in bytes (8 bits) or in words (16 bits) to or from even or odd addresses. each dma channel maintains both a 20-bit source and destina- tion pointer which can be optionally incremented or decremented after each data transfer (by one or two depending on byte or word transfers). each data transfer consumes 2 bus cycles (a minimum of 8 clocks), one cycle to fetch data and the other to store data. timer/counter unit the m80c186xl provides three internal 16-bit pro- grammable timers. two of these are highly flexible and are connected to four external pins (2 per timer). they can be used to count external events, time ex- ternal events, generate nonrepetitive waveforms, etc. the third timer is not connected to any external pins, and is useful for real-time coding and time de- lay applications. in addition, the third timer can be used as a prescaler to the other two, or as a dma request source. interrupt control unit the m80c186xl can receive interrupts from a num- ber of sources, both internal and external. the m80c186xl has 5 external and 2 internal interrupt sources (timer/couners and dma). the internal in- terrupt controller serves to merge these requests on a priority basis, for individual service by the cpu. enhanced mode operation in compatible mode the m80c186xl operates with all the features of the nmos 80186, with the excep- tion of 8087 support (i.e. no math coprocessing is possible in compatible mode). queue-status infor- mation is still available for design purposes other than 8087 support. all the enhanced mode features are completely masked when in compatible mode. a write to any of the enhanced mode registers will have no effect, while a read will not return any valid data. in enhanced mode, the m80c186xl will operate with power-save, dram refresh, and numerics co- processor support in addition to all the compatible mode features. if connected to a math coprocessor, this mode will be invoked automatically. without an npx, this mode can be entered by tying the reset output signal from the m80c186xl to the test /busy in- put. queue-status mode the queue-status mode is entered by strapping the rd pin low. rd is sampled at reset and if low, the m80c186xl will reconfigure the ale and wr pins to be qs0 and qs1 respectively. this mode is available on the m80c186xl in both compatible and enhanced modes. 12
m80c186xl dram refresh control unit the refresh control unit (rcu) automatically gen- erates dram refresh bus cycles. the rcu operates only in enhanced mode. after a programmable peri- od of time, the rcu generates a memory read re- quest to the biu. if the address generated during a refresh bus cycle is within the range of a properly programmed chip select, that chip select will be acti- vated when the biu executes the refresh bus cycle. power-save control the m80c186xl, when in enhanced mode, can en- ter a power saving state by internally dividing the processor clock frequency by a programmable fac- tor. this divided frequency is also available at the clkout pin. all internal logic, including the refresh control unit and the timers, have their clocks slowed down by the division factor. to maintain a real time count or a fixed dram refresh rate, these peripherals must be re-programmed when entering and leaving the pow- er-save mode. interface for 80c187 math coprocessor in enhanced mode, three of the mid-range memory chip selects are redefined according to table 2 for use with the 80c187. the fourth chip select, mcs2 functions as in compatible mode, and may be pro- grammed for activity with ready logic and wait states accordingly. as in compatible mode, mcs2 will func- tion for one-fourth a programmed block size. table 2. mcs assignments compatible enhanced mode mode mcs0 pereq processor extension request mcs1 error npx error mcs2 mcs2 mid-range chip select mcs3 nps numeric processor select once test mode to facilitate testing and inspection of devices when fixed into a target system, the m80c186xl has a test mode available which allows all pins to be placed in a high-impedance state. once stands for ``on circuit emulation''. when placed in this mode, the m80c186xl will put all pins in the high-imped- ance state until reset. the once mode is selected by tying the ucs and the lcs low during reset. these pins are sam- pled on the low-to-high transition of the res pin. the ucs and the lcs pins have weak internal pull- up resistors similar to the rd and test /busy pins to guarantee once mode is not entered inadver- tently during normal operation. lcs and ucs must be held low at least one clock after res goes high to guarantee entrance into once mode. 13
m80c186xl absolute maximum ratings * case temperature under bias b 55 cto a 125 c storage temperature b 65 cto a 150 c voltage on any pin with respect to ground b 1.0v to a 7.0v /package power dissipation 1w not to exceed the maximum allowable die tempera- ture based on thermal resistance of the package. notice: this data sheet contains information on products in the sampling and initial production phases of development. it is valid for the devices indicated in the revision history. the specifications are subject to change without notice. * warning: stressing the device beyond the ``absolute maximum ratings'' may cause permanent damage. these are stress ratings only. operation beyond the ``operating conditions'' is not recommended and ex- tended exposure beyond the ``operating conditions'' may affect device reliability. notice: the specifications are subject to change without notice. dc characteristics t c eb 55 cto a 125 c, v cc e 5v g 10% symbol parameter min max units test conditions v il input low voltage (except x1) b 0.5 0.2 v cc b 0.3 v v il1 clock input low voltage (x1) b 0.5 0.6 v v ih input high voltage 0.2 v cc a 0.9 v cc a 0.5 v (all except x1 and res ) v ih1 input high voltage (res ) 3.0 v cc a 0.5 v v ih2 clock input high voltage (x1) 3.9 v cc a 0.5 v v ol output low voltage 0.45 v i ol e 2.5 ma (s0, 1, 2) i ol e 2.0 ma (others) v oh output high voltage 2.4 v cc vi oh eb 2.4 ma @ 2.4v (4) v cc b 0.5 v cc vi oh eb 200 m a @ v cc b 0.5 (4) i cc power supply current 100 ma @ 20 mhz, b 55 c v cc e 5.5v (3) 90 ma @ 16 mhz, b 55 c v cc e 5.5v (3) 80 ma @ 12.5 mhz, b 55 c v cc e 5.5v (3) 70 ma @ 10 mhz, b 55 c v cc e 5.5v (3) i li input leakage current g 10 m a @ 0.5 mhz, 0.45v s v in s v cc i lo output leakage current g 10 m a @ 0.5 mhz, 0.45v s v out s v cc (1) v clo clock output low 0.45 v i clo e 4.0 ma 14
m80c186xl dc characteristics (continued) t c eb 55 cto a 125 c, v cc e 5v g 10% symbol parameter min max units test conditions v cho clock output high v cc b 0.5 v i cho eb 500 m a c in input capacitance 10 pf @ 1 mhz (2) c io output or i/o capacitance 20 pf @ 1 mhz (2) notes: 1. pins being floated during hold or by invoking the once mode. 2. characterization conditions are a) frequency e 1 mhz; b) unmeasured pins at gnd; c) v in at a 5.0v or 0.45v. this parameter is not tested. 3. current is measured with the device in reset with x1 and x2 driven and all other non-power pins open. 4. rd /qsmd , ucs , lcs , mcs0 /pereq, mcs1 /error and test /busy pins have internal pullup devices. loading some of these pins above i oh eb 200 m a can cause the m80c186xl to go into alternative modes of operation. see the section on local bus controller and reset for details. 15
m80c186xl ac characteristics major cycle timings (read cycle) t c eb 55 cto a 125 c, v cc e 5v g 10% all timings are measured at 1.5v and 100 pf loading on clkout unless otherwise noted. all output test conditions are with c l e 50 pf. for ac tests, input v il e 0.45v and v ih e 2.4v except at x1 where v ih e v cc b 0.5v. values conditions test symbol parameter m80c186xl m80c186xl12 unit min max min max m80c186xl general timing requirements (listed more than once) t dvcl data in setup (a/d) 15 15 ns t cldx data in hold (a/d) 3 3 ns m80c186xl general timing responses (listed more than once) t chsv status active delay 3 45 3 35 ns t clsh status inactive delay 3 46 3 35 ns t clav address valid delay 3 44 3 36 ns t clax address hold 0 0 ns t cldv data valid delay 3 40 3 36 ns t chdx status hold time 10 10 ns t chlh ale active delay 30 25 ns t lhll ale width t clcl b 15 t clcl b 15 ns t chll ale inactive delay 30 25 ns t avll address valid to ale low t clch b 18 t clch b 15 ns equal loading t llax address hold from ale t chcl b 15 t chcl b 15 ns equal inactive loading t avch address valid to clock high 0 0 ns t claz address float delay t clax 30 t clax 25 ns t clcsv chip-select active delay 3 42 3 33 ns t cxcsx chip-select hold from t clch b 10 t clch b 10 ns equal command inactive loading t chcsx chip-select inactive delay 3 35 3 30 ns t dxdl den inactive to dt/r low 0 0 ns equal loading t cvctv control active delay 1 3 44 3 37 ns t cvdex den inactive delay 3 44 3 37 ns t chctv control active delay 2 3 44 3 37 ns t cllv lock valid/invalid delay 3 40 3 37 ns m80c186xl timing responses (read cycle) t azrl address float to rd active 0 0 ns t clrl rd active delay 3 44 3 37 ns t rlrh rd pulse width 2t clcl b 30 2t clcl b 25 ns t clrh rd inactive delay 3 44 3 37 ns t rhlh rd inactive to ale high t clch b 14 t clch b 14 ns equal loading t rhav rd inactive to address t clcl b 15 t clcl b 15 ns equal active loading 16
m80c186xl ac characteristics major cycle timings (read cycle) t c eb 55 cto a 125 c, v cc e 5v g 10% all timings are measured at 1.5v and 100 pf loading on clkout unless otherwise noted. all output test conditions are with c l e 50 pf. for ac tests, input v il e 0.45v and v ih e 2.4v except at x1 where v ih e v cc b 0.5v. values conditions test symbol parameter m80c186xl16 m80c186xl20 unit min max min max m80c186xl general timing requirements (listed more than once) t dvcl data in setup (a/d) 15 10 ns t cldx data in hold (a/d) 3 3 ns m80c186xl general timing responses (listed more than once) t chsv status active delay 1 31 1 25 ns t clsh status inactive delay 1 30 1 25 ns t clav address valid delay 1 33 1 27 ns t clax address hold 0 0 ns t cldv data valid delay 1 33 1 27 ns t chdx status hold time 10 10 ns t chlh ale active delay 20 20 ns t lhll ale width t clcl b 15 t clcl b 15 ns t chll ale inactive delay 20 20 ns t avll address valid to ale low t clch b 15 t clch b 10 ns equal loading t llax address hold from ale t chcl b 15 t chcl b 10 ns equal inactive loading t avch address valid to clock high 0 0 ns t claz address float delay t clax 20 t clax 20 ns t clcsv chip-select active delay 1 30 1 25 ns t cxcsx chip-select hold from t clch b 10 t clch b 10 ns equal command inactive loading t chcsx chip-select inactive delay 1 25 1 20 ns t dxdl den inactive to dt/r low 0 0 ns equal loading t cvctv control active delay 1 1 31 1 22 ns t cvdex den inactive delay 1 31 1 22 ns t chctv control active delay 2 1 31 1 22 ns t cllv lock valid/invalid delay 1 35 1 22 ns m80c186xl timing responses (read cycle) t azrl address float to rd active 0 0 ns t clrl rd active delay 1 31 1 27 ns t rlrh rd pulse width 2t clcl b 25 2t clcl b 20 ns t clrh rd inactive delay 1 31 1 27 ns t rhlh rd inactive to ale high t clch b 14 t clch b 14 ns equal loading t rhav rd inactive to address t clcl b 15 t clcl b 15 ns equal active loading 17
m80c186xl ac characteristics major cycle timings (write cycle) t c eb 55 cto a 125 c, v cc e 5v g 10% all timings are measured at 1.5v and 100 pf loading on clkout unless otherwise noted. all output test conditions are with c l e 50 pf. for ac tests, input v il e 0.45v and v ih e 2.4v except at x1 where v ih e v cc b 0.5v. values conditions test symbol parameter m80c186xl m80c186xl12 unit min max min max m80c186xl general timing responses (listed more than once) t chsv status active delay 3 45 3 35 ns t clsh status inactive delay 3 46 3 35 ns t clav address valid delay 3 44 3 36 ns t clax address hold 0 0 ns t cldv data valid delay 3 40 3 36 ns t chdx status hold time 10 10 ns t chlh ale active delay 30 25 ns t lhll ale width t clcl b 15 t clcl b 15 ns t chll ale inactive delay 30 25 ns t avll address valid to ale low t clch b 18 t clch b 15 ns equal loading t llax address hold from ale t chcl b 15 t chcl b 15 ns equal inactive loading t avch address valid to clock high 0 0 ns t cldox data hold time 3 3 ns t cvctv control active delay 1 3 44 3 37 ns t cvctx control inactive delay 3 44 3 37 ns t clcsv chip-select active delay 3 42 3 33 ns t cxcsx chip-select hold from t clch b 10 t clch b 10 ns equal command inactive loading t chcsx chip-select inactive delay 3 35 3 30 ns t dxdl den inactive to dt/r low 0 0 ns equal loading t cllv lock valid/invalid delay 3 40 3 37 ns m80c186xl timing responses (write cycle) t wlwh wr pulse width 2t clcl b 30 2t clcl b 25 ns t whlh wr inactive to ale high t clch b 14 t clch b 14 ns equal loading t whdx data hold after wr t clcl b 34 t clcl b 20 ns equal loading t whdex wr inactive to den inactive t clch b 10 t clch b 10 ns equal loading 18
m80c186xl ac characteristics major cycle timings (write cycle) t c eb 55 cto a 125 c, v cc e 5v g 10% all timings are measured at 1.5v and 100 pf loading on clkout unless otherwise noted. all output test conditions are with c l e 50 pf. for ac tests, input v il e 0.45v and v ih e 2.4v except at x1 where v ih e v cc b 0.5v. values conditions test symbol parameter m80c186xl16 m80c186xl20 unit min max min max m80c186xl general timing responses (listed more than once) t chsv status active delay 1 31 1 25 ns t clsh status inactive delay 1 30 1 25 ns t clav address valid delay 1 33 1 27 ns t clax address hold 0 0 ns t cldv data valid delay 1 33 1 27 ns t chdx status hold time 10 10 ns t chlh ale active delay 20 20 ns t lhll ale width t clcl b 15 t clcl b 15 ns t chll ale inactive delay 20 20 ns t avll address valid to ale low t clch b 15 t clch b 10 ns equal loading t llax address hold from ale t chcl b 15 t chcl b 10 ns equal inactive loading t avch address valid to clock high 0 0 ns t cldox data hold time 1 1 ns t cvctv control active delay 1 1 31 1 25 ns t cvctx control inactive delay 1 31 1 25 ns t clcsv chip-select active delay 1 30 1 25 ns t cxcsx chip-select hold from t clch b 10 t clch b 10 ns equal command inactive loading t chcsx chip-select inactive delay 1 25 1 20 ns t dxdl den inactive to dt/r low 0 0 ns equal loading t cllv lock valid/invalid delay 1 35 1 22 ns m80c186xl timing responses (write cycle) t wlwh wr pulse width 2t clcl b 25 2t clcl b 20 ns t whlh wr inactive to ale high t clch b 14 t clch b 14 ns equal loading t whdx data hold after wr t clcl b 20 t clcl b 15 ns equal loading t whdex wr inactive to den inactive t clch b 10 t clch b 10 ns equal loading 19
m80c186xl ac characteristics major cycle timings (interrupt acknowledge cycle) t c eb 55 cto a 125 c, v cc e 5v g 10% all timings are measured at 1.5v and 100 pf loading on clkout unless otherwise noted. all output test conditions are with c l e 50 pf. for ac tests, input v il e 0.45v and v ih e 2.4v except at x1 where v ih e v cc b 0.5v. values conditions test symbol parameter m80c186xl m80c186xl12 unit min max min max m80c186xl general timing requirements (listed more than once) t dvcl data in setup (a/d) 15 15 ns t cldx data in hold (a/d) 3 3 ns m80c186xl general timing responses (listed more than once) t chsv status active delay 3 45 3 35 ns t clsh status inactive delay 3 46 3 35 ns t clav address valid delay 3 44 3 36 ns t avch address valid to clock high 0 0 ns t clax address hold 0 0 ns t cldv data valid delay 3 40 3 36 ns t chdx status hold time 10 10 ns t chlh ale active delay 30 25 ns t lhll ale width t clcl b 15 t clcl b 15 ns t chll ale inactive delay 30 25 ns t avll address valid to ale low t clch b 18 t clch b 15 ns equal loading t llax address hold to ale t chcl b 15 t chcl b 15 ns equal inactive loading t claz address float delay t clax 30 t clax 25 ns t cvctv control active delay 1 3 44 3 37 ns t cvctx control inactive delay 3 44 3 37 ns t dxdl den inactive to dt/r low 0 0 ns equal loading t chctv control active delay 2 3 44 3 37 ns t cvdex den inactive delay 3 44 3 37 ns (non-write cycles) t cllv lock valid/invalid delay 3 40 3 37 ns 20
m80c186xl ac characteristics major cycle timings (interrupt acknowledge cycle) t c eb 55 cto a 125 c, v cc e 5v g 10% all timings are measured at 1.5v and 100 pf loading on clkout unless otherwise noted. all output test conditions are with c l e 50 pf. for ac tests, input v il e 0.45v and v ih e 2.4v except at x1 where v ih e v cc b 0.5v. values conditions test symbol parameter m80c186xl16 m80c186xl20 unit min max min max m80c186xl general timing requirements (listed more than once) t dvcl data in setup (a/d) 15 10 ns t cldx data in hold (a/d) 1 1 ns m80c186xl general timing responses (listed more than once) t chsv status active delay 1 31 1 25 ns t clsh status inactive delay 1 30 1 25 ns t clav address valid delay 1 33 1 27 ns t avch address valid to clock high 0 0 ns t clax address hold 0 0 ns t cldv data valid delay 1 33 1 27 ns t chdx status hold time 10 10 ns t chlh ale active delay 20 20 ns t lhll ale width t clcl b 15 t clcl b 15 ns t chll ale inactive delay 20 20 ns t avll address valid to ale low t clch b 15 t clch b 10 ns equal loading t llax address hold to ale t chcl b 15 t chcl b 10 ns equal inactive loading t claz address float delay t clax 20 t clax 20 ns t cvctv control active delay 1 1 31 1 25 ns t cvctx control inactive delay 1 31 1 25 ns t dxdl den inactive to dt/r low 0 0 ns equal loading t chctv control active delay 2 1 31 1 22 ns t cvdex den inactive delay 1 31 1 22 ns (non-write cycles) t cllv lock valid/invalid delay 1 35 1 22 ns 21
m80c186xl ac characteristics software halt cycle timings t c eb 55 cto a 125 c, v cc e 5v g 10% all timings are measured at 1.5v and 100 pf loading on clkout unless otherwise noted. all output test conditions are with c l e 50 pf. for ac tests, input v il e 0.45v and v ih e 2.4v except at x1 where v ih e v cc b 0.5v. values conditions test symbol parameter m80c186xl m80c186xl12 unit min max min max m80c186xl general timing requirements (listed more than once) t chsv status active delay 3 45 3 35 ns t clsh status inactive delay 3 46 3 35 ns t clav address valid delay 3 44 3 36 ns t chlh ale active delay 30 25 ns t lhll ale width t clcl b 15 t clcl b 15 ns t chll ale inactive delay 30 25 ns t dxdl den inactive to dt/r low 0 0 ns equal loading t chctv control active delay 2 3 44 3 37 ns values conditions test symbol parametertarget m80c186xl16 m80c186xl20 unit min max min max m80c186xl general timing responses (listed more than once) t chsv status active delay 3 31 3 25 ns t clsh status inactive delay 3 30 3 25 ns t clav address valid delay 3 33 3 27 ns t chlh ale active delay 20 20 ns t lhll ale width t clcl b 15 t clcl b 15 ns t chll ale inactive delay 20 20 ns t dxdl den inactive to dt/r low 0 0 ns equal loading t chctv control active delay 2 3 31 3 22 ns 22
m80c186xl ac characteristics clock timings t c eb 55 cto a 125 c, v cc e 5v g 10% all timings are measured at 1.5v and 100 pf loading on clkout unless otherwise noted. all output test conditions are with c l e 50 pf. for ac tests, input v il e 0.45v and v ih e 2.4v except at x1 where v ih e v cc b 0.5v. values conditions test symbol parameter m80c186xl m80c186xl12 unit min max min max m80c186xl clkin requirements (1) t ckin clkin period 50 % 40 % ns t clck clkin low time 20 % 16 % ns 1.5v (2) t chck clkin high time 20 % 16 % ns 1.5v (2) t ckhl clkin fall time 5 5 ns 3.5 to 1.0v t cklh clkin rise time 5 5 ns 1.0 to 3.5v m80c186xl clkout timing t cico clkin to clkout skew 25 21 ns t clcl clkout period 100 % 80 % ns t clch clkout low time 0.5 t clcl b 6 0.5 t clcl b 5nsc l e 100 pf (3) t chcl clkout high time 0.5 t clcl b 6 0.5 t clcl b 5nsc l e 100 pf (4) t ch1ch2 clkout rise time 10 10 ns 1.0 to 3.5v t cl2cl1 clkout fall time 10 10 ns 3.5 to 1.0v notes: 1. external clock applied to x1 and x2 not connected. 2. t clck and t chck (clkin low and high times) should not have a duration less than 40% of t ckin . 3. tested under worst case conditions: v cc e 5.5v t c ea 125 c. 4. tested under worst case conditions: v cc e 4.5v t c eb 55 c. 23
m80c186xl ac characteristics clock timings t c eb 55 cto a 125 c, v cc e 5v g 10% all timings are measured at 1.5v and 100 pf loading on clkout unless otherwise noted. all output test conditions are with c l e 50 pf. for ac tests, input v il e 0.45v and v ih e 2.4v except at x1 where v ih e v cc b 0.5v. values conditions test symbol parameter m80c186xl16 m80c186xl20 unit min max min max m80c186xl clkin requirements (1) t ckin clkin period 31.25 % 25 % ns t clck clkin low time 13 % 10 % ns 1.5v (2) t chck clkin high time 13 % 10 % ns 1.5v (2) t ckhl clkin fall time 5 5 ns 3.5 to 1.0v t cklh clkin rise time 5 5 ns 1.0 to 3.5v m80c186xl clkout timing t cico clkin to clkout skew 17 17 ns t clcl clkout period 62.5 50 ns t clch clkout low time 0.5 t clcl b 5 0.5 t clcl b 5nsc l e 100 pf (3) t chcl clkout high time 0.5 t clcl b 5 0.5 t clcl b 5nsc l e 100 pf (4) t ch1ch2 clkout rise time 10 8 ns 1.0 to 3.5v t cl2cl1 clkout fall time 10 8 ns 3.5 to 1.0v notes: 1. external clock applied to x1 and x2 not connected. 2. t clck and t chck (clkin low and high times) should not have a duration less than 40% of t ckin . 3. tested under worst case conditions: v cc e 5.5v. t c ea 125 c. 4. tested under worst case conditions: v cc e 4.5v. t c eb 55 c. 24
m80c186xl ac characteristics ready, peripheral and queue status timings t c eb 55 cto a 125 c, v cc e 5v g 10% all timings are measured at 1.5v and 100 pf loading on clkout unless otherwise noted. all output test conditions are with c l e 50 pf. for ac tests, input v il e 0.45v and v ih e 2.4v except at x1 where v ih e v cc b 0.5v. values conditions test symbol parameter m80c186xl m80c186xl12 unit min max min max m80c186xl ready and peripheral timing requirements (listed more than once) t srycl synchronous ready (srdy) 15 15 ns transition setup time (1) t clsry srdy transition hold time (1) 15 15 ns t arych ardy resolution transition 15 15 ns setup time (2) t clarx ardy active hold time (1) 15 15 ns t arychl ardy inactive holding time 15 15 ns t arylcl asynchronous ready 25 25 ns (ardy) setup time (1) t invch intx, nmi, test /busy, 15 15 ns tmr in setup time (2) t invcl drq0, drq1 setup time (2) 15 15 ns m80c186xl peripheral and queue status timing responses t cltmv timer output delay 40 33 ns t chqsv queue status delay 37 32 ns notes: 1. to guarantee proper operation. 2. to guarantee recognition at clock edge. 25
m80c186xl ac characteristics ready, peripheral, and queue status timings t c eb 55 cto a 125 c, v cc e 5v g 10% all timings are measured at 1.5v and 100 pf loading on clkout unless otherwise noted. all output test conditions are with c l e 50 pf. for ac tests, input v il e 0.45v and v ih e 2.4v except at x1 where v ih e v cc b 0.5v. values conditions test symbol parameter m80c186xl16 m80c186xl20 unit min max min max m80c186xl ready and peripheral timing requirements t srycl synchronous ready (srdy) 15 10 ns transition setup time (1) t clsry srdy transition hold time (1) 15 10 ns t arych ardy resolution transition 15 10 ns setup time (2) t clarx ardy active hold time (1) 15 10 ns t arychl ardy inactive holding time 15 10 ns t arylcl asynchronous ready 25 15 ns (ardy) setup time (1) t invch intx, nmi, test /busy, 15 10 ns tmr in setup time (2) t invcl drq0, drq1 setup time (2) 15 10 ns m80c186xl peripheral and queue status timing responses t cltmv timer output delay 27 22 ns t chqsv queue status delay 30 27 ns notes: 1. to guarantee proper operation. 2. to guarantee recognition at clock edge. 26
m80c186xl ac characteristics reset and hold/hlda timings t c eb 55 cto a 125 c, v cc e 5v g 10% all timings are measured at 1.5v and 100 pf loading on clkout unless otherwise noted. all output test conditions are with c l e 50 pf. for ac tests, input v il e 0.45v and v ih e 2.4v except at x1 where v ih e v cc b 0.5v. values conditions test symbol parameter m80c186xl m80c186xl12 unit min max min max m80c186xl reset and hold/hlda timing requirements t resin res setup 15 15 ns t hvcl hold setup (1) 15 15 ns m80c186xl general timing responses (listed more than once) t claz address float delay t clax 30 t clax 25 ns t clav address valid delay 3 44 3 36 ns m80c186xl reset and hold/hlda timing responses t clro reset delay 40 33 ns t clhav hlda valid delay 3 40 3 33 ns t chcz command lines float delay 40 33 ns t chcv command lines valid delay 44 36 ns (after float) note: 1. to guarantee recognition at next clock. 27
m80c186xl ac characteristics reset and hold/hlda timings t c eb 55 cto a 125 c, v cc e 5v g 10% all timings are measured at 1.5v and 100 pf loading on clkout unless otherwise noted. all output test conditions are with c l e 50 pf. for ac tests, input v il e 0.45v and v ih e 2.4v except at x1 where v ih e v cc b 0.5v. values conditions test symbol parameter m80c186xl16 m80c186xl20 unit min max min max m80c186xl reset and hold/hlda timing requirements t resin res setup 15 15 ns t hvcl hold setup (1) 15 10 ns m80c186xl general timing responses (listed more than once) t claz address float delay t clax 20 t clax 20 ns t clav address valid delay 1 33 1 22 ns m80c186xl reset and hold/hlda timing responses t clro reset delay 27 22 ns t clhav hlda valid delay 1 25 1 22 ns t chcz command lines float delay 28 25 ns t chcv command lines valid delay 32 26 ns (after float) note: 1. to guarantee recognition at next clock. 28
m80c186xl ac characteristics 271276 7 notes: 1. status inactive in state preceding t 4 . 2. if latched a 1 and a 2 are selected instead of pcs5 and pcs6 , only t clcsv is applicable. 3. for write cycle followed by read cycle. 4. t 1 of next bus cycle. 5. changes in t-state preceding next bus cycle if followed by write. figure 5. read cycle waveforms 29
m80c186xl ac characteristics 271276 8 notes: 1. status inactive in state preceding t 4 . 2. if latched a 1 and a 2 are selected instead of pcs5 and pcs6 , only t clcsv is applicable. 3. for write cycle followed by read cycle. 4. t 1 of next bus cycle. 5. changes in t-state preceding next bus cycle if followed by read, inta, or halt. figure 6. write cycle waveforms 30
m80c186xl ac characteristics 271276 9 notes: 1. status inactive in state preceding t 4 . 2. the data hold time lasts only until inta goes inactive, even if the inta transition occurs prior to t cldx (min). 3. inta occurs one clock later in slave mode. 4. for write cycle followed by interrupt acknowledge cycle. 5. lock is active upon t 1 of the first interrupt acknowledge cycle and inactive upon t 2 of the second interrupt acknowl- edge cycle. 6. changes in t-state preceding next bus cycle if followed by write. figure 7. interrupt acknowledge cycle waveforms 31
m80c186xl ac characteristics 271276 10 note: 1. for write cycle followed by halt cycle. figure 8. software halt cycle waveforms 32
m80c186xl waveforms 271276 11 figure 9. clock waveforms 271276 12 figure 10. reset waveforms 271276 13 figure 11. synchronous ready (srdy) waveforms 33
m80c186xl ac characteristics 271276 19 figure 12. asynchronous ready (ardy) waveforms 271276 14 figure 13. peripheral and queue status waveforms 34
m80c186xl ac characteristics 271276 20 figure 14. hold/hlda waveforms (entering hold) 271276 15 figure 15. hold/hlda waveforms (leaving hold) 35
m80c186xl explanation of the ac symbols each timing symbol has from 5 to 7 characters. the first character is always a `t' (stands for time). the other characters, depending on their positions, stand for the name of a signal or the logical status of that signal. the following is a list of all the characters and what they stand for. a: address ary: asynchronous ready input c: clock output ck: clock input cs: chip select ct: control (dt/r , den ,...) d: data input de: den h: logic level high out: input (drq0, tim0, . . . ) l: logic level low or ale o: output qs: queue status (qs1, qs2) r: rd signal, reset signal s: status (s0 ,s1 ,s2 ) sry: synchronous ready input v: valid w: wr signal x: no longer a valid logic level z: float examples: t clav e time from clock low to address valid t chlh e time from clock high to ale high t clcsv e time from clock low to chip select valid 36
m80c186xl derating curves typical output delay capacitive derating 271276 16 figure 16. capacitive derating curve typical rise and fall times for ttl voltage levels 271276 17 figure 17. ttl level rise and fall times for output buffers typical rise and fall times for cmos voltage levels 271276 18 figure 18. cmos level rise and fall times for output buffers 37
m80c186xl m80c186xl execution timings a determination of m80c186xl program execution timing must consider the bus cycles necessary to prefetch instructions as well as the number of exe- cution unit cycles necessary to execute instructions. the following instruction timings represent the mini- mum execution time in clock cycles for each instruc- tion. the timings given are based on the following assumptions: # the opcode, along with any data or displacement required for execution of a particular instruction, has been prefetched and resides in the queue at the time it is needed. # no wait states or bus holds occur. # all word-data is located on even-address bound- aries. all jumps and calls include the time required to fetch the opcode of the next instruction at the destination address. all instructions which involve memory accesses can require one or two additional clocks above the mini- mum timings shown due to the asynchronous hand- shake between the bus interface unit (biu) and exe- cution unit. with a 16-bit biu, the m80c186xl has sufficient bus performance to ensure that an adequate number of prefetched bytes will reside in the queue most of the time. therefore, actual program execution time will not be substantially greater than that derived from adding the instruction timings shown. 38
m80c186xl instruction set summary function format clock comments cycles data transfer mov e move: register to register/memory 1000100w modreg r/m 2/12 register/memory to register 1000101w modreg r/m 2/9 immediate to register/memory 1100011w mod000 r/m data data if w e 1 12 13 8/16-bit immediate to register 1011w reg data data if w e 1 3 4 8/16-bit memory to accumulator 1010000w addr-low addr-high 8 accumulator to memory 1010001w addr-low addr-high 9 register/memory to segment register 10001110 mod0reg r/m 2/9 segment register to register/memory 10001100 mod0reg r/m 2/11 push e push: memory 11111111 mod110 r/m 16 register 01010 reg 10 segment register 000reg110 9 immediate 011010s0 data data if s e 010 pusha e push all 01100000 36 pop e pop: memory 10001111 mod000 r/m 20 register 01011 reg 10 segment register 000reg111 (reg i 01) 8 popa e popall 01100001 51 xchg e exchange: register/memory with register 1000011w modreg r/m 4/17 register with accumulator 10010 reg 3 in e input from: fixed port 1110010w port 10 variable port 1110110w 8 out e output to: fixed port 1110011w port 9 variable port 1110111w 7 xlat e translate byte to al 11010111 11 lea e load ea to register 10001101 modreg r/m 6 lds e load pointer to ds 11000101 modreg r/m (mod i 11) 18 les e load pointer to es 11000100 modreg r/m (mod i 11) 18 lahf e load ah with flags 10011111 2 sahf e store ah into flags 10011110 3 pushf e push flags 10011100 9 popf e pop flags 10011101 8 shaded areas indicate instructions not available in 8086/8088 microsystems. 39
m80c186xl instruction set summary (continued) function format clock comments cycles data transfer (continued) segment e segment override: cs 00101110 2 ss 00110110 2 ds 00111110 2 es 00100110 2 arithmetic add e add: reg/memory with register to either 000000dw modreg r/m 3/10 immediate to register/memory 100000sw mod000 r/m data data if s w e 01 4/16 immediate to accumulator 0000010w data data if w e 1 3/4 8/16-bit adc e add with carry: reg/memory with register to either 000100dw modreg r/m 3/10 immediate to register/memory 100000sw mod010 r/m data data if s w e 01 4/16 immediate to accumulator 0001010w data data if w e 1 3/4 8/16-bit inc e increment: register/memory 1111111w mod000 r/m 3/15 register 01000 reg 3 sub e subtract: reg/memory and register to either 001010dw modreg r/m 3/10 immediate from register/memory 100000sw mod101 r/m data data if s w e 01 4/16 immediate from accumulator 0010110w data data if w e 1 3/4 8/16-bit sbb e subtract with borrow: reg/memory and register to either 000110dw modreg r/m 3/10 immediate from register/memory 100000sw mod011 r/m data data if s w e 01 4/16 immediate from accumulator 0001110w data data if w e 1 3/4 8/16-bit dec e decrement register/memory 1111111w mod001 r/m 3/15 register 01001 reg 3 cmp e compare: register/memory with register 0011101w modreg r/m 3/10 register with register/memory 0011100w modreg r/m 3/10 immediate with register/memory 100000sw mod111 r/m data data if s w e 01 3/10 immediate with accumulator 0011110w data data if w e 1 3/4 8/16-bit neg e change sign register/memory 1111011w mod011 r/m 3/10 aaa e ascii adjust for add 00110111 8 daa e decimal adjust for add 00100111 4 aas e ascii adjust for subtract 00111111 7 das e decimal adjust for subtract 00101111 4 mul e multiply (unsigned): 1111011w mod100 r/m register-byte 2628 register-word 3537 memory-byte 3234 memory-word 4143 shaded areas indicate instructions not available in 8086/8088 microsystems. 40
m80c186xl instruction set summary (continued) function format clock comments cycles arithmetic (continued) imul e integer multiply (signed): 1111011w mod101 r/m register-byte 2528 register-word 3437 memory-byte 3134 memory-word 4043 imul e integer immediate multiply 011010s1 modreg r/m data data if s e 0 22 25/ (signed) 2932 div e divide (unsigned): 1111011w mod110 r/m register-byte 29 register-word 38 memory-byte 35 memory-word 44 idiv e integer divide (signed): 1111011w mod111 r/m register-byte 4452 register-word 5361 memory-byte 5058 memory-word 5967 aam e ascii adjust for multiply 11010100 00001010 19 aad e ascii adjust for divide 11010101 00001010 15 cbw e convert byte to word 10011000 2 cwd e convert word to double word 10011001 4 logic shift/rotate instructions: register/memory by 1 1101000w modtttr/m 2/15 register/memory by cl 1101001w modtttr/m 5 a n/17 a n register/memory by count 1100000w modtttr/m count 5 a n/17 a n ttt instruction 000 rol 001 ror 010 rcl 011 rcr 1 0 0 shl/sal 101 shr 111 sar and e and: reg/memory and register to either 001000dw modreg r/m 3/10 immediate to register/memory 1000000w mod100 r/m data data if w e 1 4/16 immediate to accumulator 0010010w data data if w e 1 3/4 8/16-bit test e and function to flags, no result: register/memory and register 1000010w modreg r/m 3/10 immediate data and register/memory 1111011w mod000 r/m data data if w e 1 4/10 immediate data and accumulator 1010100w data data if w e 1 3/4 8/16-bit or e or: reg/memory and register to either 000010dw modreg r/m 3/10 immediate to register/memory 1000000w mod001 r/m data data if w e 1 4/16 immediate to accumulator 0000110w data data if w e 1 3/4 8/16-bit shaded areas indicate instructions not available in 8086/8088 microsystems. 41
m80c186xl instruction set summary (continued) function format clock comments cycles logic (continued) xor e exclusive or: reg/memory and register to either 001100dw modreg r/m 3/10 immediate to register/memory 1000000w mod110 r/m data data if w e 1 4/16 immediate to accumulator 0011010w data data if w e 1 3/4 8/16-bit not e invert register/memory 1111011w mod010 r/m 3/10 string manipulation movs e move byte/word 1010010w 14 cmps e compare byte/word 1010011w 22 scas e scan byte/word 1010111w 15 lods e load byte/wd to al/ax 1010110w 12 stos e store byte/wd from al/ax 1010101w 10 ins e input byte/wd from dx port 0110110w 14 outs e output byte/wd to dx port 0110111w 14 repeated by count in cx (rep/repe/repz/repne/repnz) movs e move string 11110010 1010010w 8 a 8n cmps e compare string 1111001z 1010011w 5 a 22n scas e scan string 1111001z 1010111w 5 a 15n lods e load string 11110010 1010110w 6 a 11n stos e store string 11110010 1010101w 6 a 9n ins e input string 11110010 0110110w 8 a 8n outs e output string 11110010 0110111w 8 a 8n control transfer call e call: direct within segment 11101000 disp-low disp-high 15 register/memory 11111111 mod010 r/m 13/19 indirect within segment direct intersegment 10011010 segment offset 23 segment selector indirect intersegment 11111111 mod011 r/m (mod i 11) 38 jmp e unconditional jump: short/long 11101011 disp-low 14 direct within segment 11101001 disp-low disp-high 14 register/memory 11111111 mod100 r/m 11/17 indirect within segment direct intersegment 11101010 segment offset 14 segment selector indirect intersegment 11111111 mod101 r/m (mod i 11) 26 shaded areas indicate instructions not available in 8086/8088 microsystems. 42
m80c186xl instruction set summary (continued) function format clock comments cycles control transfer (continued) ret e return from call: within segment 11000011 16 within seg adding immed to sp 11000010 data-low data-high 18 intersegment 11001011 22 intersegment adding immediate to sp 11001010 data-low data-high 25 je/jz e jump on equal/zero 01110100 disp 4/13 jmp not jl/jnge e jump on less/not greater or equal 01111100 disp 4/13 taken/jmp jle/jng e jump on less or equal/not greater 01111110 disp 4/13 taken jb/jnae e jump on below/not above or equal 01110010 disp 4/13 jbe/jna e jump on below or equal/not above 01110110 disp 4/13 jp/jpe e jump on parity/parity even 01111010 disp 4/13 jo e jump on overflow 01110 000 disp 4/13 js e jump on sign 01111000 disp 4/13 jne/jnz e jump on not equal/not zero 01110101 disp 4/13 jnl/jge e jump on not less/greater or equal 01111101 disp 4/13 jnle/jg e jump on not less or equal/greater 01111111 disp 4/13 jnb/jae e jump on not below/above or equal 01110011 disp 4/13 jnbe/ja e jump on not below or equal/above 01110111 disp 4/13 jnp/jpo e jump on not par/par odd 01111011 disp 4/13 jno e jump on not overflow 01110001 disp 4/13 jns e jump on not sign 01111001 disp 4/13 jcxz e jump on cx zero 11100011 disp 5/15 loop e loop cx times 11100010 disp 6/16 loop not loopz/loope e loop while zero/equal 11100001 disp 6/16 taken/loop loopnz/loopne e loop while not zero/equal 11100000 disp 6/16 taken enter e enter procedure 11001000 data-low data-high l l e 0 15 l e 1 25 l l 1 22 a 16(n b 1) leave e leave procedure 11001001 8 int e interrupt: type specified 11001101 type 47 type 3 11001100 45 if int. taken/ into e interrupt on overflow 11001110 48/4 if int. not taken iret e interrupt return 11001111 28 bound e detect value out of range 01100010 modreg r/m 3335 shaded areas indicate instructions not available in 8086/8088 microsystems. 43
m80c186xl instruction set summary (continued) function format clock comments cycles processor control clc e clear carry 11111000 2 cmc e complement carry 11110101 2 stc e set carry 11111001 2 cld e clear direction 11111100 2 std e set direction 11111101 2 cli e clear interrupt 11111010 2 sti e set interrupt 11111011 2 hlt e halt 11110100 2 wait e wait 10011011 6 if test e 0 lock e bus lock prefix 11110000 2 nop e no operation 10010000 3 (ttt lll are opcode to processor extension) shaded areas indicate instructions not available in 8086/8088 microsystems. footnotes the effective address (ea) of the memory operand is computed according to the mod and r/m fields: if mod e 11 then r/m is treated as a reg field if mod e 00 then disp e 0 * , disp-low and disp- high are absent if mod e 01 then disp e disp-low sign-ex- tended to 16-bits, disp-high is absent if mod e 10 then disp e disp-high: disp-low if r/m e 000 then ea e (bx) a (si) a disp if r/m e 001 then ea e (bx) a (di) a disp if r/m e 010 then ea e (bp) a (si) a disp if r/m e 011 then ea e (bp) a (di) a disp if r/m e 100 then ea e (si) a disp if r/m e 101 then ea e (di) a disp if r/m e 110 then ea e (bp) a disp * if r/m e 111 then ea e (bx) a disp disp follows 2nd byte of instruction (before data if required) * except if mod e 00 and r/m e 110 then ea e disp-high: disp-low. ea calculation time is 4 clock cycles for all modes, and is included in the execution times given whenev- er appropriate. segment override prefix 0 0 1 reg 1 1 0 reg is assigned according to the following: segment reg register 00 es 01 cs 10 ss 11 ds reg is assigned according to the following table: 16-bit (w e 1) 8-bit (w e 0) 000 ax 000 al 001 cx 001 cl 010 dx 010 dl 011 bx 011 bl 100 sp 100 ah 101 bp 101 ch 110 si 110 dh 111 di 111 bh the physical addresses of all operands addressed by the bp register are computed using the ss seg- ment register. the physical addresses of the desti- nation operands of the string primitive operations (those addressed by the di register) are computed using the es segment, which may not be overridden. intel corporation, 2200 mission college blvd., santa clara, ca 95052; tel. (408) 765-8080 printed in u.s.a./tp118/0296/2.5k/pe sm

▲Up To Search▲

Price & Availability of MA80C186XL16

	To Download MA80C186XL16 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .